IP Release Packaging Engineer/CAD

IP Release Packaging Engineer/CAD

  • Location

    Bay Area , United States

  • Sector:


  • Job type:


  • Salary:


  • Contact:

    Matt Hezlep

  • Job ref:


  • Published:

    about 1 year ago

  • Expiry date:


One of my top consulting clients is looking for an IP Release Packaging Engineer/CAD in the Bay Area to work on contract with the following skillset:

Job Description: We are looking for a CAD/Automation Engineer (CW) with some experience in digital design and/or verification. This engineer will develop an IP packaging and qualification flow for internal use and external delivery.

•    Scripting and automation of design database qualification and packaging
•    Creation of packaging flow of design and verification components
•    Checks and validation of package consistency
•    Propagation of packaging flow requirements with internal IP teams
•    Support and maintenance of qualification tools and scripts (lint, CDC, sim)
•    Running of stand-alone IP testbench for qualification
•    Initial debug of failures and issues and work w/ IP teams for resolution
•    Maintaining package and release timelines for various projects
•    Working with cross functional teams (DV/Arch/Design/FW) to insure quality and completeness of release collateral


  • Minimum Qualifications:
     5-10 years of experience in CAD automation and/or RTL Design\Verification
    •    Experience with development of fully automated flows
    •    Strong Python scripting skills
    •    Strong unix,shell,make skills
    •    Strong familiarity with git usage and branching
    •    Experience w/ Spyglass or similar linting platforms
    •    Familiarity w/ Jenkins or other CI platforms
  • Preferred Qualification:
    •    Knowledge of System Verilog UVM and vertical tetsbench integration
    •    Knowledge of low level HW/SW interaction and debug
    •    Knowledge of multi CPU and debug architectures
    •    Experience with coverage merging across simulation and emulation
    •    Experience with Power Aware and Gate Level Netlist in Emulation
    •    Experience with Gate Level Simulations