Austin, United States
27 days ago
One of my top consulting clients is looking for a ASIC Design Verification Engineer in the Bay Area to work on contract with the following skillset:
- Work with researchers and architects defining verification methodologies for each of the different core IP.
- Define and track detailed test plans for the different modules and top levels.
- Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
- Keep track of coverage metrics and bugs encountered and fixed. Implement self-testing directed and random tests.
- Support post silicon bringup and debug activities.
- Ability to communicate clearly
- 2+ years of System Verilog OVM/UVM DV experience.
- Knowledge of Python, Perl, shell scripting.
- Knowledge with assertions (SVA) or others.
- Knowledge of digital ASICs design flows.
- Bachelor’s degree in Electrical Engineering or Computer Science or equivalent experience.
Nice to haves:
- C, C++ coding, debugging experience.
- Experience as a digital design engineer.
- Experience with low power design.
- FPGA implementation and debug experience.
- Self-motivated and team player.
- Masters in Electrical Engineering or Computer Science.