ASIC Design Verification Engineer

ASIC Design Verification Engineer

  • Location

    San Francisco, United States

  • Sector:


  • Job type:


  • Salary:


  • Contact:

    Matt Hezlep

  • Contact email:


  • Job ref:


  • Published:

    7 months ago

  • Expiry date:


  • Consultant:


This is a long term contracted consulting job for one of our top social media clients in the Bay Area.  They are looking for a ASIC Design Verification Engineer with the following experience to come and join their growing team!

Minimum Qualifications:

  • 5+ years of experience in RTL Design and Verification area of which 2+ years of experience in SoC Design Verification and HW/SW verification
  • 2+ years of GPU or Video IP Verification Knowledge of System Verilog UVM and vertical testbench integration
  • Knowledge of low level HW/SW interaction and debug Knowledge of multi CPU and debug architectures Experience with development of fully automated flows


  • Experience with low level SW debug - disasm, Tarmac, trace
  • Experience with GPU architecture Experience with coresight architecture
  • Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
  • Experience with coverage merging across simulation and emulation
  • Experience with Power Aware, low-power validation and Gate Level Netlist in Emulation
  • Experience with development of fully automated flows
  • Experience with Gate Level Simulations
  • Python scripting